The present invention relates to a communication device; and, more particularly, to a carrier frequency recovery apparatus capable of simultaneously reducing frequency offset and phase error.
In a typical coherent digital communication system including a transmitter and a receiver, the transmitter modulates a data by using a carrier frequency and transmits a modulated data to the receiver. At the receiver, the modulated data as a received signal is demodulated to extract the data by carrying out a carrier frequency recovery operation. At this time, whether it is possible to extract data or not depends on the carrier frequency recovery, so that the carrier frequency recovery is very important regardless of data error.
A conventional carrier frequency recovery circuit including a PLL (phase locked loop) structure carries out a carrier frequency recovery operation by gradually reducing a phase difference between a received signal and an output signal from a VCO (voltage controlled oscillator) , until the phase difference therebetween becomes below a predetermined value.
In such a carrier frequency recovery circuit, a first assumption is that a frequency difference between the received signal and the signal outputted from the VCO is not large, and additional circuits need to be added in order for this. A second assumption is that a phase rotation error may occur due to a phase noise even after recovering the carrier frequency, i.e., after obtaining a locked phase.
The conventional carrier frequency recovery circuit employs a scheme that covers only a carrier phase. In that case, however, an automatic frequency control (AFC) unit is used to reduce a frequency offset of a signal outputted from the carrier frequency recovery circuit. For example, in case where a signal from the carrier frequency recovery circuit has a frequency offset of 100 kHz or more, the AFC unit reduces the frequency offset of the signal to a predetermined value until the carrier phase can be recovered. At this time, the AFC unit is generally constituted with differentiators, multipliers, adders and the like, so that a chip size is increased.
It is, therefore, an object of the present invention to provide a carrier frequency recovery circuit for simultaneously reducing a frequency offset and a phase error without using an AFC unit.
In accordance with an aspect of the present invention, there is provided a carrier frequency recovery apparatus for simultaneously reducing a frequency offset and a phase error, comprising: a phase detection means for estimating a phase error of an I-channel and Q-channel signals having a frequency offset; a select signal generating means for receiving the phase error and generating a select signal; a first loop filter means for attenuating the phase error by a predetermined range; a second loop filter means for attenuating the phase error in a range narrower than the first loop filter means; an addition means for adding the output value of the first loop filter means to an output value of the second loop filter means; a multiplexing means for selectively outputting an output value of the first loop filter means or an output value of the addition means in response to the select signal; and a voltage-controlled oscillation means for storing and outputting cosine and sine signals corresponding to an output value of the multiplexing means, wherein the cosine and sine signals are used to correct the frequency offset of the I-channel and Q-channel signals.
In accordance with another aspect of the present invention, there is provided a method for simultaneously reducing a frequency offset and a phase error, comprising the steps of: a) estimating a phase error of an I-channel and Q-channel signals having a predetermined frequency offset; b) attenuating the phase error by a first range; c) outputting cosine and sine signals corresponding to an attenuating phase error; d) correcting the I-channel and Q-channel signals by using the cosine and sine signals; e) repeating the steps a) to d) until a select signal is enabled; f) if the select signal is enabled, attenuating a phase error of a corrected I-channel and Q-channel signals by a second range narrower than the first range; g) outputting cosine and sine signals corresponding to the attenuated phase error; h) correcting the I-channel and Q-channel signals; and i) repeating the steps f) to h) until the select signal is disabled.